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for free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. for small orders, phone 408-737-7600 ext. 3468. ________________general description the max1664 integrates power-supply and backplane drive circuitry for active-matrix thin-film-transistor (tft) liq- uid crystal displays. included are a single-output, pulse- width-modulation boost converter (0.25 switch), a dual-output (positive and negative) gate-driver supply using one inductor, an lcd backplane driver, and a sim- ple phase-locked loop to synchronize all three outputs. high switching frequency (1mhz nominal) and phase- locked operation allow the use of small, minimum- height external components while maintaining low output noise. a +2.8v to +5.5v input voltage range allows operation with any logic supply. output voltages are adjustable to +5.5v (dc-dc 1) and to +28v and -10v (dc-dc 2). the negative output voltage can be adjusted to -20v with additional components. also included are a logic-level shutdown and a ?eady?out- put (rdy) that signals when all three outputs are in reg- ulation. the boost-converter operating frequency can be set at 16, 24, or 32 times the backplane clock. this flexibility allows a high dc-dc converter frequency to be used with lcd backplane clock rates ranging from 20khz to 72khz. the max1664 is supplied in a 1.1mm-high tssop package. ________________________applications lcd modules lcd panels ____________________________features ? integrates all active circuitry for three dc-dc converters ? ultra-small external components (ceramic capacitors, 2? to 5? inductors) ? dc-dc converters phase-locked to backplane frequency for lowest noise ? low operating voltage (down to +2.8v) ? adjustable output voltage from v in to +5.5v ? load currents up to 500ma ? adjustable tft gate driver output: positive, v in to +28v negative, 0 to -10v (-20v with added components) ? includes 0.35 backplane driver ? 1? shutdown current ? power-ready output signal max1664 ________________________________________________________________ maxim integrated products 1 ref fb2- in inp lx2p lx2n fb2+ pgnd2 pllc gnd fpll rdy ref shdn on off 5.5v -10v 28v bpv ss backplane driver v supply 2.8v to 5.5v bpdrv bpv dd pgnd1 fb1 lx1 bpclk max1664 typical operating circuit ___________________pin configuration 19-1356; rev 0; 4/98 part max1664cup 0? to +70? temp. range pin-package 20 tssop _______________ordering information 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 fpll lx1 pgnd1 pgnd2 ref fb1 rdy shdn top view lx2n lx2p inp bpclk fb2+ fb2- in gnd 12 11 9 10 bpv dd bpdrv bpv ss pllc max1664 tssop active-matrix liquid crystal display (amlcd) supply
max1664 active-matrix liquid cr ystal display (amlcd) supply 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v inp = 3.3v, shdn = in, v bpvdd = 4v, v bpvss = -1v, pgnd1 = pgnd2 = fpll = gnd, f bpclk = 30khz, t a = 0 c to +70 c, unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. rdy, in, bpv dd to gnd ........................................... -0.3v to +6v fb2-, pgnd1, pgnd2 to gnd .......................................... 0.3v lx1 to pgnd1 .......................................................... -0.3v to +6v bpv ss to gnd ....................................................... -3.3v to +0.3v bpvdd to bpv ss ...................................................... -0.3v to +6v bpdrv to bpv ss .................................. -0.3v to (v bpvdd + 0.3v) lx2p to inp ............................................................ -15v to +0.3v lx2n to pgnd2 ...................................................... -0.3v to +30v shdn , inp, fb1, fb2+, ref, pllc, bpclk, fpll to gnd ................................ -0.3v to (v in +0.3v) rdy sink current ................................................................ 20ma lx2p, lx2n peak switch currents ................................. 750ma continuous power dissipation (t a = +70 c) 20-pin tssop (derate 7mw/ c above+70 c) .............. 559mw operating temperature range ............................... 0 c to +70 c junction temperature ...................................................... +150 c storage temperature range ............................. -65 c to +160 c lead temperature (soldering, 10sec) ............................. +300 c fpll = in fpll = ref fpll = gnd rising edge, 2% hysteresis v lx1 = 6v fpll = ref fpll = gnd v fb1 = 1.3v v fb1+ = v fb2+ = 1.3v, v fb2- = -0.1v; i in + i inp shdn = gnd, v in = 5.5v; i in + i inp fpll = in conditions 8 x f bpclk 12 x f bpclk hz 16 x f bpclk f op2(max) maximum operating frequency v -10 0 v out2- negative output voltage range v v in 28 v out2+ positive output voltage range v 1.091 1.125 1.159 v th_rdy power-ready trip level a 1.2 1.5 1.8 i lim(lx1) lx1 peak current limit a 0.1 10 i lkg(lx1) lx1 leakage current 0.25 0.5 r on(lx1) lx1 on resistance na 100 i fb1 fb1 input bias current 16 x f bpclk operating frequency v 2.5 2.8 v uvlo v 2.8 5.5 v in input supply range undervoltage lockout threshold 24 x f bpclk hz 32 x f bpclk f op1 v v in 5.5 v out1 output voltage range ma 0.5 2 i q quiescent current a 0.01 10 i sd shutdown current units min typ max symbol parameter 0 < i lx1 < 1.2a v 1.2125 1.2500 1.275 v fb1 fb1 regulation voltage dc-dc 1 (pwm main output) dc-dc 2 (pfm)
max1664 active-matrix liquid cr ystal display (amlcd) supply _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v inp = 3.3v, shdn = in, v bpvdd = 4v, v bpvss = -1v, pgnd1 = pgnd2 = fpll = gnd, f bpclk = 30khz, t a = 0 c to +70 c, unless otherwise noted. typical values are at t a = +25 c.) v bpclk = 0 or 3.3v shdn = gnd source and sink rising edge, 40mv hysteresis shdn = gnd falling edge, 40mv hysteresis v lx2n = 28v, v lx2p = -10v v fb2+ = 1.3v, v fb2- = -0.1v conditions a 0.01 1 i in(bpclk) bpclk input current v 0.7 x v in v ih(bpclk) bpclk input high voltage v 0.3 x v in v il(bpclk) bpclk input low voltage a 80 200 i in(bpvdd) bpv dd supply current a -10 10 i lkg(bpdrv) bpdrv leakage current 0.35 0.7 r on(bpdrv) bpdrv on-resistance a 0.1 10 i shdn(bp) bpv dd shutdown current v 2.5 5.5 v vdd to vss bpv dd to bpv ss voltage range v -3 0 v bpvss bpv ss supply range v 2.5 5.5 v bpvdd bpv dd supply range mv -15 0 15 v fb2- v 1.225 1.25 1.275 v fb2+ fb2+ regulation voltage fb2- regulation voltage v 1.091 1.125 1.159 v th(rdy) fb2+ power-ready trip level mv 85 120 165 v th(rdy) fb2- power-ready trip level a 0.05 10 i lkg(lx2n) , i lkg(lx2p) lx2n, lx2p leakage current na -100 100 i fb2+ , i fb2- fb2+, fb2- input bias current 0.9 1.7 r on(lx2n) , r on(lx2p) lx2n, lx2p on-resistance units min typ max symbol parameter c pllc = 22nf r pllc = 100k c shunt = 2.2nf pllc = ref, bpclk = gnd 40 72 bpclk input frequency range 27 48 khz 20 36 f bpclk mhz 1.63 1.92 2.20 f c vco center frequency (note 1) -2 a < i ref < 50 a v 0.90 1.05 1.20 v ref(uvlo) undervoltage lockout v 1.225 1.250 1.275 v ref reference voltage (0.10 x v in ) typical hysteresis v 0.3 x v in v il( shdn ) shdn input low voltage fpll = gnd or in a 0.01 1 i in(fpll) fpll input current a 0.01 1 i in( shdn ) shdn input current v 0.7 x v in v ih( shdn ) shdn input high voltage i sink = 2ma v 0.05 0.4 v ol(rdy) rdy output low voltage v rdy = 5.5v a 0.01 1 i lkg(rdyoh) rdy output high leakage fpll = gnd fpll = ref fpll = in note 1: dc-dc 1 operates at one-half of the v co frequency (f c / 2). backplane driver pll logic signals
max1664 active-matrix liquid cr ystal display (amlcd) supply 4 _______________________________________________________________________________________ __________________________________________ t ypical operating characteristics (f bpclk = 22.5khz, fpll = gnd, l1 = 3.3 h, l2 = 4.7 h, t a = +25 c, unless otherwise noted.) 100 0 1 10 100 1000 dc-dc 1 efficiency vs. load current (v out1 = +5v) 20 max1664 toc01 load current (ma) efficiency (%) 40 60 80 90 10 30 50 70 v in = 3v v in = 4.5v 100 0 1 10 100 dc-dc 2 efficiency vs. load current (v out2- = -5v) 20 10 max1664 toc02 load current (ma) efficiency (%) 40 30 60 70 50 80 90 v out2+ unloaded v in = 5v v in = 3.3v 100 0 1 10 100 dc-dc 2 efficiency vs. load current (v out2+ = +15v) 20 10 max1664 toc03 load current (ma) efficiency (%) 40 30 60 70 50 80 90 v out2- unloaded v in = 5v v in = 3.3v 10mv/div v out1 ripple max1664 toc04 i out1 = 250ma, l = 3.3 m h 500ns/div v out2 100mv/ div v out2+ ripple max1664 toc05 2 m s/div v out2+ = 15v, v in = 3.3v, i load = 9ma, c out2 = 0.22 m f, ac coupled v out2- 50mv/ div v out2- ripple max1664 toc06 5 m s/div v out2- = -5v, v in = 3.3v, i load = 5ma, c out2- = 0.47 m f, ac coupled
max1664 active-matrix liquid cr ystal display (amlcd) supply _______________________________________________________________________________________ 5 t ypical operating characteristics (continued) (f bpclk = 22.5khz, fpll = gnd, l1 = 3.3 h, l2 = 4.7 h, t a = +25 c, unless otherwise noted.) v out2- = -5v, i load = 5ma, c out2- = 0.47 m f a: v out2- , 200mv/div, ac coupled b: v in , 3v to 4v v out2- line-transient response a b max1664 toc09 200mv/ div 500mv/ div 2ms/div v out1 = 5v, v in = 3.3v, c out1 = 20 m f a: v out1 , 50mv/div, ac coupled b: i out1 , 25ma to 225ma, 100ma/div v out1 load-transient response a b max1664 toc10 50mv/ div 100ma/ div 2ms/div 0 400 200 800 600 1200 1000 1400 0 20 30 10 40 50 60 70 80 90 internal fet on-resistance vs. temperature max1664 toc 11 temperature (?) internal fet on-resistance (m w ) lx2n lx2p bpdrv n-channel lx1 bpdrv p-channel 300 0 0.001 0.01 0.1 1 bpdrv rise and fall time vs. load capacitance max1664 toc12 load capacitance ( m f) rise/fall time (ns) 100 200 250 50 150 c load from bpdrv to gnd rise time fall time v out1 = 5v, i load = 250ma, c out1 = 20 m f a: v out1 , 50mv/div, ac coupled b: v in , 3v to 4v v out1 line-transient response a 50mv/ div 500mv/ div 2ms/div b max1664 toc07 v out2+ = 15v, i load = 5ma, c out2+ = 0.22 m f a: v out2+ , 200mv/div, ac coupled b: v in , 3v to 4v v out2+ line-transient response a b max1664 toc08 200mv/ div 500mv/ div 2ms/div
max1664 active-matrix liquid cr ystal display (amlcd) supply 6 _______________________________________________________________________________________ t ypical operating characteristics (continued) (f bpclk = 22.5khz, fpll = gnd, l1 = 3.3 h, l2 = 4.7 h, t a = +25 c, unless otherwise noted.) v in = 3.3v; v out2+ = 15v/8ma, v out2- = -5v/10ma note: lx2n, lx2p pulses are synched to dc-dc 1 dc-dc 2 switching waveforms discontinuous conduction v lx2n v lx2p i l2 5v/div 500ma/ div 1 m s/div 5v/div c load = 10,000pf bpclk to bpdrv falling delay bpclk bpdrv 2v/div 5v/div 100ns/div max1664 toc14 5v/div 2v/div bpdrv bpclk 100ns/div bpclk to bpdrv rising delay max1664 toc14(a)) c load = 10,000pf 0 0.4 0.2 1.0 0.8 0.6 1.6 1.4 1.2 1.8 0 2 1 3 4 5 6 no-load supply current vs. input voltage max1664 toc15 input voltage (v) no-load supply current (ma) includes all external component currents 5v/div 2v/div 5v/div 5v/div 10v/div 5v/div shdn v ref v out2- v out2+ rdy v out1 500 m s/div out-of-shutdown sequence max1664 toc16(a) 5v/div 500ma/div v lx1 i li i out1 = 300ma, l1 = 3.3 m h 500ns/div dc-dc 1 switching waveforms max1664 toc17(a)
max1664 active-matrix liquid cr ystal display (amlcd) supply _______________________________________________________________________________________ 7 pll compensation. connect compensation network as in figure 4. pllc 9 backplane driver negative supply. typically connected to pgnd1. may be connected to a separate supply. bpv ss 10 backplane driver output bpdrv 11 backplane driver positive supply. typically connected to v out1 of dc-dc 1. may be connected to a separate supply. bpv dd 12 backplane driver clock input. see table 1 for input frequency ranges. bpclk 13 analog ground. connect to pgnd1 and pgnd2. see supply connections and layout section. gnd 5 supply input to the ic. the input voltage range is +2.8v to +5.5v. in 6 regulator feedback input for negative output, dc-dc 2. regulates to 0v nominal. fb2- 7 regulator feedback input for positive output, dc-dc 2. regulates to 1.25v nominal. fb2+ 8 internal reference output. connect a 0.22 f capacitor from this pin to gnd. ref can source up to 50 a. ref 4 regulator feedback input, dc-dc 1. regulates to 1.25v nominal. fb1 3 pin ready indicator output, dc-dc 1 and dc-dc 2. open-drain n-channel output becomes high impedance when all three outputs are within 10% of regulation. rdy 2 shutdown input. drive low to enter shutdown mode. drive high or connect to in for normal operation. all ic sections are off when shdn is low. shdn 1 function name power ground 1. connect to pgnd2. source of internal lx1 n-channel mosfet. pgnd1 18 drain of internal lx1 n-channel mosfet lx1 19 sets the bpclk input frequency range for pll synchronization. connect to gnd, ref, or in. see table 1. fpll 20 dc-dc 2 power input. source of internal lx2p p-channel mosfet. inp 14 drain of internal lx2p p-channel mosfet lx2p 15 drain of internal lx2n n-channel mosfet lx2n 16 power ground 2. connect to pgnd1. source of internal lx2n n-channel mosfet. pgnd2 17 ______________________________________________________________ pin description
max1664 active-matrix liquid cr ystal display (amlcd) supply 8 _______________________________________________________________________________________ _______________ detailed description the max1664 combines power supply and backplane drive circuitry for active matrix thin-film-transistor (tft) liquid crystal displays (lcd) into one ic. included are a pulse-width-modulation (pwm) boost converter, a dual- output (positive and negative) converter using one inductor, an lcd backplane driver, and a phase- locked loop (pll) to synchronize all three outputs to the backplane clock. a high switching frequency (1mhz nominal) and phase- locked operation allow the use of small, minimum- height external components while maintaining low output noise. output voltages are adjustable to +5.5v (dc-dc 1) and to +28v and -10v (dc-dc 2). the nega - tive output voltage can be set to as low as -20v with additional components. the frequency ratio between the dc-dc 1 converter and the backplane clock can be set to 16, 24, or 32. this flexibility allows high dc-dc converter frequencies to be used with lcd backplane clock rates ranging from 20khz to 72khz. start-up at start-up, both converters remain disabled until v ref reaches 90% of its nominal value. v out1 is activated first. once v out1 is regulated, v out2- is enabled. v out2+ is held at 0 until v out2- is within 90% of its reg - ulation target. all three outputs power up in a similar order when power is applied or when coming out of shutdown. see the out-of-shutdown sequence photo in the typical operating characteristics section. dc-dc 1 boost converter dc-dc 1 uses a current-mode boost pwm architecture to produce a positive regulated voltage, adjustable from 3v to 5.5v (but not less than v in ). this converter uses an internal n-channel mosfet with a maximum on-resistance of 0.5 . cycle-by-cycle peak current lim - iting protects the switch under fault conditions. upon start-up, dc-dc 1 is the first converter to be enabled. backplane driver bpv ss bpdrv bpv dd pgnd1 fb1 lx1 v supply 2.8v to 5.5v v out1 5.5v shdn ref 1.25v ref phase det vco ? 4 ? 2 ? n fpll bpclk pllc pgnd2 fb2+ lx2n dc-dc 2 dc-dc 1 lx2p inp in fb2- ref v out2- -10v v out2+ 28v in ref gnd gnd rdy max1664 figure 1. functional diagram
max1664 active-matrix liquid cr ystal display (amlcd) supply _______________________________________________________________________________________ 9 fixed-frequency, current-mode operation ensures that the switching noise exists only at the operating frequen - cy and its harmonics. the switching frequency is phase locked to the backplane clock input. table 1 illustrates the possible switching-frequency options. dc-dc 2 dual outputs dc-dc 2 uses a synchronized, fixed on-time pfm architecture to provide the positive and negative output voltages that allow the driver ics to turn the tft gates on and off. when pulses occur, they are synchronized to dc-dc 1, thereby minimizing converter interactions and subharmonic interference. the dc-dc 2 inductor current is always discontinuous, enabling the dual outputs to be regulated independent - ly. this allows one output to be at 100% load while the other is at no load. dc-dc 2 operation in normal operation, dc-dc 2 alternates between charging the negative and positive outputs (figure 1). during the first half-cycle of the pfm clock period, both the n-channel and p-channel mosfets turn on, apply - ing the input supply across inductor l2. this causes the inductor current to ramp up at a rate proportional to v inp . during the second half-cycle, the p-channel mosfet turns off and the inductor transfers its energy into the negative output filter capacitor. assuming that the energy transfer is completed during this second half-cycle and the inductor current ramps down to zero, the process is repeated for the positive output during the next clock cycle. during the first half of the second clock cycle, both the n-channel and p- channel mosfets turn on again. the current in the inductor again rises at the same rate. during the sec - ond half of the second clock cycle, the n-channel mosfet is turned off and this time the inductor energy transfers to the positive output filter capacitor. during conditions of heavy loads, dc-dc 2 will contin - ue to operate in this manner, alternately delivering pulses to the negative and positive outputs. for lighter loads, the controller may skip one or more cycles of either polarity, thereby keeping the outputs in regula - tion. see table 1 for the relationship between the maxi - mum dc-dc 2 pulse frequency and the backplane clock frequency. outputs with low step-up or inversion ratios for dc-dc 2 output voltage setpoints, which require minimum step-up or inversion ratios (for example, v out+ < 6v or v out- > -3v, when v inp = 5v), more than one half-cycle may be required to transfer the inductor energy to the appropriate output filter capaci - tor. in such cases, subsequent conversion cycles are delayed, as necessary, by one or more pfm clock cycles to preserve discontinuous mode operation. backplane driver the max1664 provides a low-impedance backplane dri - ver, as shown in figure 1, that level-translates the bpclk signal from a logic level to bpv dd /bpv ss levels. the backplane driver consists of an n-channel/p-channel complementary pair of high-current mosfets. these devices drive bpdrv to either bpv dd or bpv ss when bpclk goes either high or low, respectively. the switch - es have a maximum on-resistance of 0.7 with a typical propagation delay of 50ns. power for the backplane dri - ver can be taken from the output of dc-dc 1, v out1 , as shown in the typical operating circuit . phase-locked loop the max1664 contains an on-board pll to synchronize the pwm and pfm converter clocks to the backplane clock (figure 2). this will minimize noise and interfer - ence. the pll is a frequency-multiplying type, generat - ing a nominal 1mhz clock signal for dc-dc 1 and a nominal 500khz clock for dc-dc 2. three input fre - quency ranges, spanning 20khz to 72khz, permit syn - chronization over a broad range of backplane clock input frequencies while maintaining optimal conversion frequencies (table 1). fpll f bpclk (khz) f dc-dc 1 (khz) f dc-dc 2 max (khz) f dc-dc 1 : f bpclk f dc-dc 2 max : f bpclk n* in 40 to 72 640 to 1152 320 to 576 16:1 8:1 32 ref 27 to 48 640 to 1152 320 to 576 24:1 12:1 48 gnd 20 to 36 640 to 1152 320 to 576 32:1 16:1 64 table 1. switching frequency options * see figure 2
max1664 active-matrix liquid cr ystal display (amlcd) supply 10 ______________________________________________________________________________________ the heart of the pll is the vco, which is trimmed to a nominal frequency of 1.92mhz for a control voltage (at the pllc pin) of 1.250v. this high-frequency internal clock is divided digitally with a division ratio selected by pin-strapping fpll to gnd, ref, or in. this divided clock is compared to the backplane clock by an inter - nal phase comparator (rising-edge triggered). the phase detector in turn adjusts the vco control voltage until the two frequencies (and phases) match. this feedback loop is compensated at the pllc pin. in some applications, the backplane clock may be halt - ed for several cycles between screen scans or may not be immediately applied on power-up. the pll contains a proprietary phase-detector architecture that mini - mizes frequency error during clock dropouts of more than two cycles and re-establishes lock immediately when the clock resumes. ready indicator (rdy) the rdy pin has an open-drain output and indicates when all three outputs are in regulation. the open-drain output becomes high impedance when all three convert - er outputs are within 10% of their regulation setpoints . design pr ocedur e and ______________ component selection output voltage selection the three output voltages as well as the dc bias for the backplane clock are adjustable on the max1664, as shown in figure 3. set each output using two standard 1% resistors to form a voltage divider between the selected output and its respective feedback pin. use the following equations to calculate the resistances. dc-dc 1 output for v out1 = 5v, typical values are r2 = 100k and r1 = 301k . to set v out1 to another voltage, choose r2 = 100k and c fb1 = 50pf, and calculate r1 as follows: dc-dc 2 positive output for v out2+ = 15v, typical values are r8 = 49.9k and r7 = 549k . to set v out2+ to another voltage, choose r8 = 49.9k and calculate r7 as follows: dc-dc 2 negative output for the negative output voltage, the fb2- threshold volt - age is 0. for v out2- = -5v, typical values are r5 = 49.9k and r6 = 200k . to set v out2+ to another volt - age, choose r5 = 49.9k and calculate r6 as follows: dc bias for the backplane driver for v dcbias = v bpvdd /2, typical values are r3 = r4 = 100k . to set the dc bias to a different value, choose r4 and calculate r3 as follows: r3 r4 v - v v - v - 1 bpvdd bpvss dcbias bpvss = ? ? ? ? r6 r5 v v out2 - ref = r7 r8 v v - 1 out2 fb2 = ? ? ? ? + + r1 r2 v v - 1 out1 fb1 = ? ? ? ? phase detector vco ? 4 ? 2 pllc ? n* in ref bpclk *see table 1 for selected values of n. dc-dc 1 r pllc c pllc c shunt dc-dc 2 gnd figure 2. internal pll operation within the max1664 bpv dd c fb1 r2 r1 fb2+ fb2- bpdrv fb1 r5 r6 v out2- r7 r8 ref bpv ss c c v out1 v out2+ r3 dc bias r4 max1664 figure 3. output voltage selection
max1664 active-matrix liquid cr ystal display (amlcd) supply ______________________________________________________________________________________ 11 inductor selection the optimum inductor value for l1 is 3.3 h, as shown in figure 4. inductors with less than 300m dc series resistance are recommended to achieve the highest efficiency. using a larger value for l1 (e.g., 4.7 h) increases the output current capability of dc-dc 1 (by reducing the peak ripple current) at the expense of size and the additional output filter capacitance needed for loop stability. for dc-dc 2, at large input voltages (i.e., 5v) and low switching frequencies (i.e., 400khz), the value of l2 should be increased (e.g., 6.8 h or 10 h) to limit the peak current. in some cases it may be necessary to reduce the value of l2 to increase the output current capability of dc-dc 2 (table 2). the relationship between input voltage, output voltage, switching frequency, induc - tor value, and maximum load current for dc-dc 2 is com - plex and nonlinear. this relationship is summarized in table 2. the l2 equation is as follows: where: internal mosfet on-resistance: r on(lx2p) = r on(lx2n) = 0.9 typical external inductor dc resistance: r l2 = 0.3 typical inductor peak current: i peak = 700ma (750ma absolute maximum) due to the max1664? high switching frequency, induc - tors with a high-frequency core material such as ferrite are recommended. powdered iron compounds are not recommended due to their higher core losses. typical small-size, low-profile inductors include the ils-3825 (dale electronics-vishay) and the clq61b (sumida). these inductors are primarily used for dc-dc converters with low height requirements. see table 3 for more information on manufacturers who provide low-profile inductors. l2 v - r r r (i ) 2 i x 2 f inp on(lx2p) on(lx2n) l2 peak peak dc - dc 1 > + + [ ] ( ) ref fb2- in inp lx2p lx2n fb2+ r8 49.9k r7 549k r6 200k r5 49.9k d3 d2 l2 4.7 m h pgnd2 pllc gnd fpll rdy ref shdn on off v out1 5.5v 2.2 m f 3 x 10 m f 0.22 m f 22nf 100k 2.2nf 0.22 m f 0.47 m f 50pf 2 x 10 m f 10 m f 10 m f 2.2 m f 33 w 0.47 m f 3.3 m h r1 301k r2 100k r3 100k r4 100k v out2- -5v v out2+ 15v bpv ss backplane driver v supply 2.8v to 5.5v bpdrv bpv dd pgnd1 fb1 lx1 bpclk max1664 figure 4. detailed typical operating circuit
max1664 12 ______________________________________________________________________________________ diode selection the max1664? high switching frequency requires fast diodes. schottky diodes such as the mbr0520l and mbr0540l (motorola) are recommended because they have the necessary power ratings in a low-height sod- 123 package. also recommended is the mbrm5817 which is 1.1mm high. use a schottky diode with a for - ward current rating greater than: for the positive output of dc-dc 2, use a schottky diode with a voltage rating that exceeds v out2+ . for the negative output, use a schottky diode with a rating that exceeds v in + v out2- . see table 3 for more information on schottky diode manufacturers. filter capacitor selection an output filter capacitor? esr and size can greatly influence a switching converter? output ripple, as shown in the following equation. v i x r i t c dc - dc 1 t 1 f v v - v v v dc - dc 2 t 1 2 f ripple(pk pk) peak esr out on out on dc - dc 1 out1 f in out1 f on dc - dc 1 - @ + ? ? ? ? = + + ? ? ? ? = . i i v v f out out in > 0 9 table 2. typical dc-dc 2 operation * note: absolute maximum peak current at lx2p and lx2n is 750ma. active matrix liquid cr ystal display (amlcd) supply inductor peak current* (ma) f dc-dc 2(max) (khz) i out2-(max) (ma) i out2+(max) (ma) l2 ( h) f bpclk (khz) v in (v) v out2- (v) v out2+ (v) 500 480 15 10 4.7 30.0 5.0 -10 +20 550 400 18 10 4.7 25.0 5.0 -10 +20 640 360 20 11 4.7 22.5 5.0 -10 +20 679 480 17 10 2.7 30.0 4.5 -10 +20 450 480 12 8 4.7 30.0 4.5 -10 +20 500 400 14 8 4.7 25.0 4.5 -10 +20 580 360 16 9 4.7 22.5 4.5 -10 +20 496 480 8 4 4.7 30.0 3.3 -10 +20 340 480 5 4 4.7 30.0 3.3 -10 +20 583 400 10 6 2.7 25.0 3.3 -10 +20 370 400 7 4 4.7 25.0 3.3 -10 +20 643 360 12 6 2.7 22.5 3.3 -10 +20 425 360 8 4 4.7 22.5 3.3 -10 +20 451 480 6 3 2.7 30.0 3.0 -10 +20 300 480 4 3 4.7 30.0 3.0 -10 +20 530 400 8 4 2.7 25.0 3.0 -10 +20 340 400 5 2 4.7 25.0 3.0 -10 +20 585 360 10 5 2.7 22.5 3.0 -10 +20 385 360 6 3 4.7 22.5 3.0 -10 +20 600 360 43 20 4.7 22.5 5.0 -5 +15 550 360 35 15 4.7 22.5 4.5 -5 +15 643 360 27 10 2.7 22.5 3.3 -5 +15 425 360 19 7 4.7 22.5 3.3 -5 +15 585 360 23 8 2.7 22.5 3.0 -5 +15 375 360 15 6 4.7 22.5 3.0 -5 +15
ceramic capacitors are recommended because they have low esr and the lowest profile. typical ceramic capacitors are the c3225x5r series from tdk and jmk325 series from taiyo yuden. see table 3 for more information on the manufacturers who provide surface- mount ceramic capacitors. pll compensation in most applications, the recommended compensation component values shown in figure 4 will give optimal system performance. if no backplane clock is used, connect pllc to ref. __________ ___ applications infor mation increasing v out above 5.5v for v out1 output voltages above 5.5v, connect the supplemental charge pump circuit shown in figure 5. the connection shown supplies a 10v 150ma output, but other voltages from 2 x v in to 10v can be set by selecting the appropriate values for r1 and r2 (see dc-dc 1 output section). c2?4 are shown as parallel combinations of 3.3 f ceramic capacitors so that a 1.1mm height restriction can be met. if height is not restricted, then larger values can be used instead of parallel capacitor combinations. 3.3v to -20v charge-pump configuration for applications requiring negative voltages down to -20v, an inverting charge-pump block can be added to the v out2- output (figure 6). typical values for c f and c out are 0.47 f to 1 f and 4.7 f to 10 f, respective - ly. as a general rule, c out should be ten times greater than c f . this circuit operates as follows: 1) during the first pfm cycle, the voltage at v1 is charged by inductor l2 to some fraction of its final steady-state voltage, in the normal manner described in the d etailed d escription . 2) during the first half of subsequent pfm cycles, pin lx2p is pulled to v inp , and capacitor c f is charged to (v inp + v 1 - v d ), where v d is a diode forward voltage. 3) during subsequent second half-cycles when lx2p flies negatively below v1, capacitor c f transfers some of its energy to output capacitor c out , which then is charged to a negative voltage of approxi - mately (v inp + 2 x v 1 - 2x v d ). 4) this process continues until v out reaches the desired voltage, as determined by the ratio of the fb2- feedback resistors. 5) during steady-state (in-regulation) operation, the magnitude of the voltage at lx2p is equal to ( v out / 2 - v inp / 2 + v d ), which must be limited to less than 10v. max1664 active-matrix liquid cr ystal display (amlcd) supply ______________________________________________________________________________________ 13 manufacturer phone fax dale inductors (605) 668-4131 (605) 665-1627 sumida usa (847) 956-0666 (847) 956-0702 central semiconductor (516) 435-1110 (516) 435-1824 international rectifier (310) 322-3331 (310) 322-3232 tdk (847) 390-4373 (847) 390-4428 vishay/vitramon (203) 268-6261 (203) 452-5670 table 3. component manufacturers max1664 lx1 c3 3.3 m f (x6) c4 3.3 m f (x2) r2 13k d1, d2, d3?mbrm5817 c1, c2, c3?ll ceramic types r1 91k c2 3.3 m f (x2) 50pf d2 33 w in inp d3 d1 v 1 10v 150ma v supply 2.8v to 3.6v pgnd1 fb1 c1 3.3 m f (x2) 3.3 m h 0.47 m f figure 5. charge pump configuration to increase v out1 above 5.5v. motorola (602) 303-5454 (602) 994-6430 marcon/united chemicon (847) 696-2000 (847) 696-9278 taiyo yuden (408) 573-4150 (408) 573-4159 inductors diodes ceramic capacitors
max1664 active-matrix liquid cr ystal display (amlcd) supply 14 ______________________________________________________________________________________ figure 7a. max1664 component placement guide figure 7b. max1664 pc board layout?omponent side 1.0" 1.0" supply connections and layout the max1664 performs both precision analog and high-power switching functions. carefully plan supply connections, bypassing, and layout. bypass in and inp with a 33 isolation resistor (r9, figure 4) between them. in addition, sufficient low-esr bypassing must be provided on the inp bus to ensure stability of dc-dc 1. a solid ground plane under the power components, with a separate ground plane under the analog nodes, is highly recommended. these ground planes should be connected at a single, quiet point. analog reference and feedback signals should be referred to and routed over the analog ground plane. figure 7 shows a typical layout using separate ground planes. ref r5 r6 r7 r8 fb2- lx2p l2 lx2n fb2+ d3 d2 d5 d4 c f v1 pgnd2 0.47 m f 0.22 m f c out 4.7 m f v out2- -20v v out2+ 28v max1664 figure 6. v out2 - voltage-doubler charge pump
max1664 active-matrix liquid cr ystal display (amlcd) supply ______________________________________________________________________________________ 15 figure 7c. max1664 pc board layout?older side 1.0" transistor count: 838 ___________________ chip infor mation
max1664 active-matrix liquid cr ystal display (amlcd) supply maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________ maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 1998 maxim integrated products printed usa is a registered trademark of maxim integrated products. ________________________________________________________ package infor mation tssop.eps
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs max1664 part number table notes: see the max1664 quickview data sheet for further information on this product family or download the max1664 full data sheet (pdf, 264kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 4. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis max1664c up tssop;20 pin;4.4mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-2 * 0c to +70c rohs/lead-free: no materials analysis max1664c up-t tssop;20 pin;4.4mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-2 * 0c to +70c rohs/lead-free: no materials analysis MAX1664EUP tssop;20 pin;4.4mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-2 * -40c to +85c rohs/lead-free: no materials analysis MAX1664EUP-t tssop;20 pin;4.4mm dwg: 21-0066i (pdf) use pkgcode/variation: u20-2 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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